In English

FPGA-Based Demonstrator for Real-Time Evaluation of a Fiber-Optic Communication System

Fredrik Åkerlund
Göteborg : Chalmers tekniska högskola, 2017. 75 s.
[Examensarbete på avancerad nivå]

When the speed of serial transmission of data increases, it is important that the biterror rate does not increase correspondingly. One way to maintain a low bit error rate is to use forward-error correcting codes for finding and correcting erroneous bits. This Master’s Thesis describes the development of an FPGA system that acts as the physical layer in a fiber-optic communication system with bit-error correcting circuits using Bose–Chaudhuri–Hocquenghem codes. The FPGA transceiver system will allow for further research on, e.g., what level of error correction is suitable for physical coding sublayers.

Nine transceiver systems were developed in this thesis, with different error-finding and correcting Bose–Chaudhuri–Hocquenghem circuits. This report describes how the support logic needed was designed and how the hardware peripherals of the FPGA were enabled. The status of a running system is monitored in real-time from a program running on a PC, e.g., the current measured bit-error rate and the attenuation of the fiber-optic channel. The real-time program was used with the systems in a simple experiment to show how the error correction worked when the fiber-optic signal was attenuated.

Nyckelord: FPGA, ASIC, forward error correction, BCH, bit error rate.



Publikationen registrerades 2017-10-17. Den ändrades senast 2017-10-17

CPL ID: 252552

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