In English

Fault Vulnerability and Countermeasures in Digital Systems for Airborne and Space Applications

Andrée Centervall ; Marko Russegren Sladic
Göteborg : Chalmers tekniska högskola, 2016. 77 s.
[Examensarbete på avancerad nivå]

This thesis project explores and tests different combinations of fault tolerant techniques in order to counteract radiation-induced faults in static random access memory (SRAM)-based field-programmable gate array (FPGA). The use of FPGAs has become very popular for critical airborne systems and space applications during the last decade due to their outstanding performance, high flexibility, low non-recurring engineering (NRE) cost and fast time to market (TTM) compared to other customized approaches.

Radiation-induced faults, such as single event upsets (SEUs) and single event transients (SETs), do not permanently damage transistors or circuits but can still cause severe system failures. These faults can be experienced at both sea level and higher altitudes. However, these type of faults are more common at higher altitudes due to higher radiation levels. This poses a substantial threat to mission-critical FPGA-based applications used in airborne systems.

Many researches conducted over the years have presented mitigation techniques such as triple modular redundancy (TMR) to be successful for reducing the chances of failures in SRAM-based FPGAs due to radiation-induced faults. However TMR comes with an increased area cost since three identical modules are actively running the same design. The purpose of this thesis project is to individually test other fault mitigation techniques as well as combinations of different techniques in order to achieve high reliability while minimizing the overhead area and overall system cost.

The hardware adopted for this thesis project consists of a Kintex-7 FPGA board from Xilinx. The simulated radiation-induced faults are injected into relevant parts of the hardware in order to test the reliability of the proposed fault mitigation techniques.

The simulations show great results and the obtained reliability during tests follow the expected theoretically calculated values. The results also show the impact that the techniques has on design area and overall power consumption. Furthermore, the trade-offs between the different mitigation techniques studied in this thesis are presented.

Nyckelord: Fault Tolerance, SRAM-based FPGA, Fault Mitigation Techniques, Single Event Effect (SEE), Single Event Upset (SEU), Single Event Transient (SET), Triple modular redundancy (TMR), Error Correcting Code (ECC), Time-redundancy (TR), Active Partial Reconfiguration (APR)



Publikationen registrerades 2016-09-12. Den ändrades senast 2016-09-12

CPL ID: 241656

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