In English

Hard-decision Staircase Decoder in 28-nm Fully-Depleted Silicon-on-Insulator

Elma Hurtic ; Henri Lillmaa
Göteborg : Chalmers tekniska högskola, 2016. 54 s.
[Examensarbete på avancerad nivå]

The continuous advancements in optical communication channels have propelled the development of new error-correcting codes, e.g., staircase codes, which belong to a class of hard-decision algebraic codes. The staircase code is a new in-line error-correcting code that promises near-capacity performance. In this Master’s Thesis BCH component codes and staircase codes are analysed in MATLAB. A bit-parallel BCH component code decoder is described in VHDL and synthesised in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) library. Based on synthesis and simulation, the area and power consumption of staircase decoders for 100 Gbps throughput are estimated.

Nyckelord: staircase-decoder, 28nm-technology, error-correcting codes, forward error correction, BCH-decoder, MATLAB, VHDL.

Publikationen registrerades 2016-06-29. Den ändrades senast 2016-06-29

CPL ID: 238595

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