In English

Design of 28nm FD-SOI CMOS 800MS/s SAR ADC for wireless applications

Victor Åberg
Göteborg : Chalmers tekniska högskola, 2016. 130 s.
[Examensarbete på avancerad nivå]

As user expectations for higher bandwidth continue to rise, new techniques are required. One such is the massive-Multiple Input Multiple Output (MIMO), building on dozens or hundreds of antennas all having their own antenna. Making compact, low cost transceivers then becomes essential. Silicon technology fulfils the cost while suffering in terms of performance which needs to be compensated for by active pre-distortion which require an Analog-to-Digital Converter (ADC). This converter must have low power consumption, small footprint and achieve high sample rates in order to be useful.

This work tries to fulfil these demands by implementing a Successive-Approximation- Register (SAR) Analog-to-Digital Converter (ADC) in a 28nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide Semiconductor (CMOS) process. The converter has been implemented based on the principle of alternating comparators in combination with a redundantly scaled Capacitive Digital-to-Analog Converter (CDAC) that help increase the operation speed. The implementation also includes additional circuitry in order to support testing of the circuit.

The implemented ADC shows an SNDR = 38.4 dB at a sample rate of 800MS/s. The converter consumes 1.1mW of power while doing this which results in a FoMW = 20.3 fJ/conversion step. This Figure of Merit (FoM) is among the lowest reported for high speed ADC.

Nyckelord: SAR, ADC, Redundant scaling, Alternating comparator, 800MS/s



Publikationen registrerades 2016-06-27. Den ändrades senast 2016-06-27

CPL ID: 238305

Detta är en tjänst från Chalmers bibliotek