# Construction of a low-ripple inverter with accurate phase control for calibration of measurement equipment

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For the design of an electric power system, knowledge of the parameters of all the components is essential. Especially the transformers are an important part of this. It is therefore important that the measurement equipment for determining these values is accurate. In no-load operation, the transformer mainly consumes reactive power. A small error in the measurement of the power angle therefore gives a large error in the active power calculation. The Technical Research Institute of Sweden, SP, performs calibrations of these measurement systems. Calibrations are done by measuring a reference voltage and generating a current in a secondary circuit with a controllable phase shift. The voltage and current make up a virtual power and are measured by the reference instrument and by the equipment to be calibrated. This thesis describes the work of constructing a single-phase full-bridge converter for inverter operation with accurate phase control of the current in the secondary circuit relative to the sinusoidal reference voltage. A CompactRIO™ system from National Instruments is used to control the converter through pulse-width modulation (PWM). An analogueto- digital converter (ADC) module is used to sample the reference signal and a digital I/O module outputs the PWM signals. A phase-locked loop (PLL) algorithm estimates the phase of the sampled reference voltage to use in the generation of the PWM signals. Three different PLLs have been implemented with LabVIEW™ code on the FPGA chip of the CompactRIO™ system. The three PLLs are the inverse Park PLL (IP-PLL) based on the synchronous reference frame, the enhanced PLL (E-PLL) based on the gradient descent method and the KF-PLL based on the Kalman filter. Both the E-PLL and the KF-PLL are also based on models for estimating specific signal components. With the basic configurations, the IP-PLL shows superior performance in simulations with dc offset and low-order harmonic in the input signal. This is due to its low-pass filters. While the standard deviation in the phase error of the IP-PLL was 50 rad it was 350 rad for the E-PLL and 570 rad for the KF-PLL with a dc offset at 1.8 % of the fundamental amplitude in the input signal. With a third harmonic at 10 % of the fundamental amplitude, the standard deviations of the phase errors were 50.3 rad, 776 rad and 889 rad for the IP-PLL, the E-PLL and the KF-PLL respectively. By extending the E-PLL and the KF-PLL to include estimation of dc-offset and harmonics, these steady-state errors are completely eliminated. However, especially the KF-PLL but also the E-PLL, is much more complex and harder to tune than the IP-PLL. When implemented on CompactRIO™ the KF-PLL including estimation of dc offset got the best results with a standard deviation in the phase error of 5.1 rad compared to 49.2 rad for the IP-PLL with minimized cut-off frequency iii of the low-pass filters for a dc offset of 0.41 % of the fundamental amplitude in the input signal. It is shown that the phase error of the complete system can be kept below a standard deviation of 600 rad, with a stable reference voltage. The pattern of the phase error however has an oscillatory shape with a frequency of about 0.12 Hz. This is thought to originate from a drift in the clock of the ADC module relative to the clock of the FPGA in the CompactRIO™ system. This must be further investigated. Additionally, the amplitude accuracy of the fundamental frequency is found to have a standard deviation of about 63 ppm, with a dc-source specified to be accurate to 50 ppm.

**Nyckelord: **PWM, full-bridge converter, IGBT, CompactRIO™, Kalman filter, PLL.

Publikationen registrerades 2014-09-09. Den ändrades senast 2015-01-19

CPL ID: 202533

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