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Improving idle power consumption in class D audio amplifiers

Tobias Lindemark ; Sebastian Andersson
Göteborg : Chalmers tekniska högskola, 2014. 87 s.
[Examensarbete på avancerad nivå]

A class D audio amplifier usually have a high efficiency for medium to high output power. However, in idle mode and for small power outputs, the efficiency drops. During idle mode, the output switches runs with a 50 % duty cycle in order to create zero volt over the load. The main task of this thesis was to investigate if the idle losses could be decreased by lowering the voltage feeding the amplifier. This without lowering the efficiency on normal operation. Three designs solutions to lower the voltage have been created and investigated. Two solutions switches between two separate rails, each at a different voltage level. The third uses a dual-polarity buck converter to feed the amplifier with just above the necessary voltage at all times. The designs were simulated in PSpice and the result analysed using both PSpice and MATLAB. It was concluded that all three solutions work as intended and lowers the idle power consumption without adding any extra loss of efficiency at normal operation. An attempt was made at implementing the buck converters on a printed circuit board. The results from the measurements performed on the prototype showed that the PWM signal generation and surrounding control circuits worked. The power path was also intact, however only DC output could be achieved for frequencies above 500 Hz.



Publikationen registrerades 2014-07-03. Den ändrades senast 2015-01-19

CPL ID: 200131

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