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Harvard
Siby, O. (2014) Implementation of a real-time computer for space applications. Göteborg : Chalmers University of Technology
BibTeX
@mastersthesis{
Siby2014,
author={Siby, Oscar},
title={Implementation of a real-time computer for space applications},
abstract={This thesis is a pre-study presenting the challenges involved in constructing an embedded instrument control unit (ICU) and an introduction of the technologies involved. The ICU is to be constructed using an FPGA implementing a GRLIB/Leon 3 soft processor and running a real-time operating system with communication through an ESA Spacewire IP core. The starting point was a Xilinx Virtex-5 Ml507 development card, the GRLIB development library and a choice between various RTOS.
A Spacewire core has been attached to the AHB bus of a Leon 3 processor design, tested on-board the Virtex-5 FPGA and verified using Grmon and testing software. From the available RTOSs Rtems was chosen as the best candidate and an Ubuntu host development environment was installed featuring the necessary software and drivers. Software was then compiled for this architecture in order to test, verify and benchmark the complete system.
The complete system is working except for a small error in the error handling within the Spacewire core and communication over Spacewire has been established with a loopback cable. The FPGA has plenty of space left after implementation of the Leon 3 design and is a good candidate when this project goes live.},
publisher={Institutionen för data- och informationsteknik (Chalmers), Chalmers tekniska högskola},
place={Göteborg},
year={2014},
note={37},
}
RefWorks
RT Generic
SR Electronic
ID 194175
A1 Siby, Oscar
T1 Implementation of a real-time computer for space applications
YR 2014
AB This thesis is a pre-study presenting the challenges involved in constructing an embedded instrument control unit (ICU) and an introduction of the technologies involved. The ICU is to be constructed using an FPGA implementing a GRLIB/Leon 3 soft processor and running a real-time operating system with communication through an ESA Spacewire IP core. The starting point was a Xilinx Virtex-5 Ml507 development card, the GRLIB development library and a choice between various RTOS.
A Spacewire core has been attached to the AHB bus of a Leon 3 processor design, tested on-board the Virtex-5 FPGA and verified using Grmon and testing software. From the available RTOSs Rtems was chosen as the best candidate and an Ubuntu host development environment was installed featuring the necessary software and drivers. Software was then compiled for this architecture in order to test, verify and benchmark the complete system.
The complete system is working except for a small error in the error handling within the Spacewire core and communication over Spacewire has been established with a loopback cable. The FPGA has plenty of space left after implementation of the Leon 3 design and is a good candidate when this project goes live.
PB Institutionen för data- och informationsteknik (Chalmers), Chalmers tekniska högskola,
LA eng
LK http://publications.lib.chalmers.se/records/fulltext/194175/194175.pdf
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