In English

Low jitter phase locked loop hardware design

Mario Deno ; Daniel Ristic
Göteborg : Chalmers tekniska högskola, 2013. 45 s.
[Examensarbete på avancerad nivå]

From the beginning the task was to implement a dedicated imaging system with fast speed, compact size and low cost for biomedical applications. The result showed in early stage that it wasn’t doable because of the hardware that was available for the thesis compared to the requirements that was made. The FPGA which was available had a clock jitter of 100ps and by calculation it showed that we could only afford 0.3175ps. By this it showed that the FPGA for this implementation could not handle the requirements. A new purpose was made which was that a PLL circuit will be designed with low clock jitter so that we go below 0.3175ps. In a PLL circuit there are four components and they are phase-frequency detector, loop filter, voltage control oscillator and a frequency divider. For the real hardware design the VCO, PFD and FD components were bought while the loop filter was designed. The VCO is the most important component in the PLL circuit because of the generation of clock jitter and phase noise in the PLL. A crystal oscillator was chosen because it is the best VCO in order to produce a low-jitter clock. We chose an ultra low phase noise VCO with a clock jitter at 0.13ps which is under the requirement which was 0.3175ps. A PFD named ADF4002 was chosen from Analog Devices which has an internal divider which is good because it will give less noise. The phase locked loop was modeled and simulated in Matlab/Simulink. The PLL was optimized so that a stable voltage swing was produced on the output of the loop filter, which then will go into the VCO:s input in order to control the output of the VCO which would be a stable frequency. This means that the output of the PLL generates a low-jitter frequency. When the simulation results were good enough a real hardware design was done.



Publikationen registrerades 2013-02-21. Den ändrades senast 2013-04-04

CPL ID: 173974

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