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**Harvard**

Beza, M. (2009) *Multilevel harmonic elimination methods for HVDC*. Göteborg : Chalmers University of Technology

** BibTeX **

@mastersthesis{

Beza2009,

author={Beza, Mebtu},

title={Multilevel harmonic elimination methods for HVDC},

abstract={In HVDC system the modulation scheme used is an important factor in achieving a
desired harmonic performance and allowable semiconductor losses. PWM patterns
with lower pulse numbers reduce semiconductor losses but make the filter design
complex and vice versa. Two-level Harmonic Elimination PWM (HEPWM) method
has been successfully applied in Voltage Source Converter based HVDC (VSCHVDC
so called HVDC Light in ABB) projects recently and achieved a good tradeoff
between the switching frequency and filtering demands.
In this thesis, therefore, the potential of using three-level HEPWM in HVDC
application to achieve lower semiconductor losses and better harmonic performance
without further increase in the filtering requirement will be investigated.
To do so, different three-level HEPWM patterns are analyzed and a suitable solution
with smallest pulse number based on the filtering requirement is chosen. The final
solution will then be compared with the two-level counterpart based on
semiconductor losses, harmonic performance and semiconductor rating requirement
and a conclusion will be made based on the results. Some drawbacks and suggested
solutions to the studied three-level topology will also be discussed.
Finally a PSCAD simulation using the developed steady state model for the new
topology will be done to verify some of the MATLAB calculation results.},

publisher={Institutionen för energi och miljö, Elteknik, Chalmers tekniska högskola},

place={Göteborg},

year={2009},

keywords={harmonic elimination, HEPWM, two-level converter, NPC converter},

note={72},

}

** RefWorks **

RT Generic

SR Electronic

ID 137754

A1 Beza, Mebtu

T1 Multilevel harmonic elimination methods for HVDC

YR 2009

AB In HVDC system the modulation scheme used is an important factor in achieving a
desired harmonic performance and allowable semiconductor losses. PWM patterns
with lower pulse numbers reduce semiconductor losses but make the filter design
complex and vice versa. Two-level Harmonic Elimination PWM (HEPWM) method
has been successfully applied in Voltage Source Converter based HVDC (VSCHVDC
so called HVDC Light in ABB) projects recently and achieved a good tradeoff
between the switching frequency and filtering demands.
In this thesis, therefore, the potential of using three-level HEPWM in HVDC
application to achieve lower semiconductor losses and better harmonic performance
without further increase in the filtering requirement will be investigated.
To do so, different three-level HEPWM patterns are analyzed and a suitable solution
with smallest pulse number based on the filtering requirement is chosen. The final
solution will then be compared with the two-level counterpart based on
semiconductor losses, harmonic performance and semiconductor rating requirement
and a conclusion will be made based on the results. Some drawbacks and suggested
solutions to the studied three-level topology will also be discussed.
Finally a PSCAD simulation using the developed steady state model for the new
topology will be done to verify some of the MATLAB calculation results.

PB Institutionen för energi och miljö, Elteknik, Chalmers tekniska högskola,

LA eng

LK http://webfiles.portal.chalmers.se/et/MSc/MebtuBihonegnBezaMSc.pdf

LK http://publications.lib.chalmers.se/records/fulltext/137754/137754.pdf

OL 30