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Olsson, M. (2010) *Test Vector Extraction Methodology For Power Integrity Analysis*. Göteborg : Chalmers University of Technology

** BibTeX **

@mastersthesis{

Olsson2010,

author={Olsson, Martin},

title={Test Vector Extraction Methodology For Power Integrity Analysis},

abstract={In order to decrease performance pessimism due to supply voltage uncertainties in
integrated circuits, detailed power integrity analysis is necessary. Knowing the worstcase
voltage drop that the circuit will encounter is a step towards this goal. The
voltage drop is input-dependent, which means the outcome depends on how the chip
is used.
In this thesis, methods to extract the worst-case clock cycle out of a microprocessor
run-trace are developed. The methods considered are based on time-based power
simulations, considering full-chip total power in several time-resolutions, frequency
based approaches using FFT and wavelets, and the spatial locality of switching activity.
SPICE voltage drop simulations are performed while considering R and L
components of the power grid, as well as decoupling capacitance and the gate switching
extracted from the run-trace.
Results show that the voltage drops found when focusing on spatial locality exceed
the previous worst-case for the chip design by a factor of 2. This method considers
the worst-case power grid node, finding the time-instance where maximum power dissipation
of its adjacent nodes coincides with the maximum power dissipation of the
chip’s CPU core.
Attempts at alleviating these sparse and localized large voltage drops are performed
through the use of skew-spreading. This method is shown to decrease the largest
voltage drop found by over 20%.
},

publisher={Institutionen för data- och informationsteknik, Datorteknik (Chalmers), Chalmers tekniska högskola},

place={Göteborg},

year={2010},

keywords={Power Integrity, IR drop, VLSI, Test Vector, VCD, L dI/dt, Skew Spreading},

note={83},

}

** RefWorks **

RT Generic

SR Electronic

ID 124128

A1 Olsson, Martin

T1 Test Vector Extraction Methodology For Power Integrity Analysis

YR 2010

AB In order to decrease performance pessimism due to supply voltage uncertainties in
integrated circuits, detailed power integrity analysis is necessary. Knowing the worstcase
voltage drop that the circuit will encounter is a step towards this goal. The
voltage drop is input-dependent, which means the outcome depends on how the chip
is used.
In this thesis, methods to extract the worst-case clock cycle out of a microprocessor
run-trace are developed. The methods considered are based on time-based power
simulations, considering full-chip total power in several time-resolutions, frequency
based approaches using FFT and wavelets, and the spatial locality of switching activity.
SPICE voltage drop simulations are performed while considering R and L
components of the power grid, as well as decoupling capacitance and the gate switching
extracted from the run-trace.
Results show that the voltage drops found when focusing on spatial locality exceed
the previous worst-case for the chip design by a factor of 2. This method considers
the worst-case power grid node, finding the time-instance where maximum power dissipation
of its adjacent nodes coincides with the maximum power dissipation of the
chip’s CPU core.
Attempts at alleviating these sparse and localized large voltage drops are performed
through the use of skew-spreading. This method is shown to decrease the largest
voltage drop found by over 20%.

PB Institutionen för data- och informationsteknik, Datorteknik (Chalmers), Chalmers tekniska högskola,

LA eng

LK http://publications.lib.chalmers.se/records/fulltext/124128.pdf

OL 30