In English

Design of a Down Converter for a Galileo Receiver

Alexander Vickberg ; Yue Wu
Göteborg : Chalmers tekniska högskola, 2010. 62 s.
[Examensarbete på avancerad nivå]

This report presents the work performed in the master thesis work "Design of a Down Converter for a Galileo Receiver". The thesis work has designed a receiver front-end down converter for the new European navigation system, Galileo. For this thesis work, the development platform Neptune-V5 VXS from Tekmicro has been used, which offers a highspeed RF sampling analogue-to-digital converter together with high-speed Xilinx Virtex-5 FPGAs. A digital down converter architecture utilizing direct RF sampling techniques is defined in this thesis work. The work also includes modeling the FPGA design in MATLAB, implementing this design in an FPGA using VHDL and targeting an ASIC implementation considering size/power constraints. Finally, through laboratory tests supported by analysis and/or system modeling the performance of key parameters have been tested.



Publikationen registrerades 2010-08-04. Den ändrades senast 2013-04-04

CPL ID: 124116

Detta är en tjänst från Chalmers bibliotek